In semiconductor processing, integrated circuits are generally formed on dies on a wafer. Processing for forming the integrated circuits can be subject to variation and error. To address this, designers can implement test structures in the wafer, such as along scribe fines between dies. The test structures and/or the integrated circuit of each die can be subjected to testing to help ensure that each integrated circuit is fully functional.
Probe testing (or wafer sorting) is a testing mechanism for testing test structures and/or integrated circuits on a wafer. Probe testing can provide electrical signals at contact pads on the wafer, and can determine whether the integrated circuit or test structure under test is functional based on responses of the integrated circuit or test structure to the electrical signals. A probe assembly can provide an interface between the wafer to be tested and a processor-based system (e.g., a computer) that provides the electrical signals and receives the responses to those electrical signals.